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ALU base instructions
All AL base instructions, including comparative and multiplication instructions,
have ARM base instruction codes of 0, 1, 2, or 3. These codes specify the format
and grouping of the AL instruction, as follows:
| Value | Group of instructions specified |
|---|
| 0 | Group I (ADC, ADD, AND, EOR, RSB, RSC, SBC and SUB) with 2 source
registers; or (if bit 7 is 1) Group III (MUL, with 2 source registers,
and MLA, with 3 source registers) |
| 1 | Group II (BIC, CMN, CMP, MOV, MVN, ORR, TEQ and TST) with only source
registers |
| 2 | Group I (ADC, ADD, AND, EOR, RSB, RSC, SBC and SUB) with 1 source
register and an immediate constant |
| 3 | Group II (BIC, CMN, CMP, MOV, MVN, ORR, TEQ and TST) with an immediate
constant |
Group I instructions are specified by the following subinstruction codes
(encoded in the top three bits of the sixth nybble):
| Value | Base instruction mnemonic |
|---|
| 0 | AND (AL2) |
| 1 | EOR (AL2) |
| 2 | SUB (AL2) |
| 3 | RSB (AL2) |
| 4 | ADD (AL2) |
| 5 | ADC (AL2) |
| 6 | SBC (AL2) |
| 7 | RSC (AL2) |
Group II instructions are specified by the following subinstruction codes
(encoded in the top three bits of the sixth nybble):
| Value | Base instruction mnemonic |
|---|
| 0 | TST (CT) |
| 1 | TEQ (CT) |
| 2 | CMP (CT) |
| 3 | CMN (CT) |
| 4 | ORR (AL2) |
| 5 | MOV (AL1) |
| 6 | BIC (AL2) |
| 7 | MVN (AL1) |
Group III instructions are specified by the following subinstruction codes
(encoded in the top three bits of the sixth nybble):
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