ARM Instruction Set: Single Register Load and Store Instructions

Assembler input:

LDR|STR[B][T] <register>,<address>

Assembler output:

High byte as standard
Bit 23 is increment flag (1 for increment)
Bit 22 is B flag
Bit 21 is ! flag, for pre-indexed, or T flag, for post-indexed
Bit 20 is load/store flag (1 for load)
Bottom five nybbles depend on base instruction grouping

If base instruction code is 4 or 5 then:

Fifth nybble is address register (use PC for PC-relative address offsets)
Fourth nybble is register to load/store
Bottom three nybbles are address offset (12-bit cardinal)

If base instruction code is 6 or 7 then:

Fifth nybble is first address register
Fourth nybble is register to load/store
Bits 7-15 (5-bit cardinal) are shift factor
Bits 5-6 are barrel shifter subinstruction code
Bit 4 is 0
Low nybble is second address register