The following codes refer to ARM base instructions. These are encoded in the
second highest nybble of the instruction.
| Value | Base instruction mnemonic |
|---|
| 0 | ADC|ADD|AND|EOR|RSB|RSC|SBC|SUB (AL2) (2 source registers)
MUL|MLA (MUL/MLA) (2 or 3 source registers) |
| 1 | BIC|CMN|CMP|MOV|MVN|ORR|TEQ|TST (AL2,AL1) (2 source registers) |
| 2 | ADC|ADD|AND|EOR|RSB|RSC|SBC|SUB (AL2) (1 source register) |
| 3 | BIC|CMN|CMP|MOV|MVN|ORR|TEQ|TST (AL2,AL1) (1 source register) |
| 4 | LDR|STR (LDR/STR) (post-indexed with constant) |
| 5 | LDR|STR (LDR/STR) (pre-indexed with constant) |
| 6 | LDR|STR (LDR/STR) (post-indexed with register) |
| 7 | LDR|STR (LDR/STR) (pre-indexed with register) |
| 8 | LDM|STM (LDM/STM) (post-indexed) |
| 9 | LDM|STM (LDM/STM) (pre-indexed) |
| A | B (B/BL) |
| B | BL (B/BL) |
| C | LDF|STF (LDF/STF) (post-indexed) |
| D | LDF|STF (LDF/STF) (pre-indexed) |
| E | ADF|MUF|SUF|RSF|DVF|RDF|POW|RPW|RMF|FML|FDV|FRD|POL (FPO2) (2 sources)
MVF|MNF|ABS|RND|SQT|LOG|LGN|EXP|SIN|COS|TAN|ASN|ACS|ATN (FPO1) (1 source)
FLT|FIX (FPRT1) (0 or 1 source registers)
WFS|RFS|WFC|RFC (FPRT0) (destination register only)
CMF|CNF|CMFE|CNFE (FPST) (0 or 1 source registers) |
| F | SWI (SWI) |
